This note is to collect ideas on doing efficient Power Management in Nuttx.
My basis is I am assuming there is a limited, but rechargeable store of coulombs - (LiIon battery or Supercapacitor) and the supply of coulombs to the store is episodic. It may be a solar panel - which has a diurnal cycle interrupted by a weather system. It might be periodic replacement of a battery supply. I use coulombs as it is the essential method for calculating energy available on SuperCapcitors. Typically battery's are quoted in mAHrs which assumes a constant voltage and is slightly easier to understand. The constant voltage is a myth that that needs to be understood for the true battery capacity.
I've used the Nuttx PM system as a starting point. It is an API and has algorithm for entering into the processors sleep/hibernation - which isn't very efficient from the point of view of minimizing coulomb consumption, and specifically doesn't address dynamic clock management. IMHO dynamic clocking is a crucial part of Arm's power management architecture. I've modified the sleep/hibernation algorithm to be more efficient, however the dynamic clock management is a major rethinking.
Some discussions on nuttx list that have taken place, and I put the context for a specific view I'm developing
https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/15347
Greg has identified a "Random Walk" algorithm for what he would like to see in Nuttx (aspirational at the time of writing)
http://www.nuttx.org/doku.php?id=wiki:nxinternal:dynamic-clocking
https://groups.yahoo.com/neo/groups/nuttx/conversations/messages/15345
Kudo's to Greg Nutt for being so dedicated to Nuttx and making it available as an open source repository.
The design I'm investigating uses a Kinetis processor, and there are NXP software tools for stetting up the clocks. In my experience the clock setup is fragile and much can go wrong with it. When something goes wrong in an Arm processor it often stops working, or generates a hard fault - both difficult to debug. Essential to have a working JTAG debugger to step through the code.
The implementation of reducing power useage is very dependent on hardware design and the processors options designed into silicon. So while its possible to define some abstractions to clocking modes, in the end the implementation is going to be in the processor domain, and going to need testing with that specific processor.
